Debug & Expansion Interfaces
The Rhino Pi IQ9N (Rhino Pi IQ9N) does not provide a 40-pin GPIO header; its expansion and debugging capabilities are provided through the SPI, I2S, and UART interfaces of the CPU and RTSS subsystems.
Interface List
| Interface | Quantity | Connector | Description |
|---|---|---|---|
| CPU-SPI | 1 | WAFER-GH1.25-6PLB | CPU subsystem SPI interface |
| RTSS-SPI | 1 | WAFER-GH1.25-6PLB | RTSS subsystem SPI interface |
| I2S | 1 | WAFER-GH1.25-4PLB | Audio interface |
| CPU-DBG | 1 | WAFER-GH1.25-4PLB | CPU debug UART |
| CPU-UART | 1 | WAFER-GH1.25-4PLB | CPU functional UART |
| RTSS-DBG | 1 | WAFER-GH1.25-4PLB | RTSS debug UART |
| RTSS-UART | 1 | WAFER-GH1.25-4PLB | RTSS functional UART |
Interface Definitions
For the positions of the SPI, I2S, and UART interfaces on the board, see the interface layout diagram in Rhino Pi IQ9N Interface Description on the first page.
SPI Interface
Both CPU-SPI and RTSS-SPI use WAFER-GH1.25-6PLB connectors (1.25mm pitch, vertical SMT, 6P):
| Pin | Signal | Description |
|---|---|---|
| 1 | VCC_3V3 | 3.3V power |
| 2 | MISO | Master in, slave out |
| 3 | MOSI | Master out, slave in |
| 4 | CLK | Clock |
| 5 | CS | Chip select |
| 6 | GND | Ground |
I2S Interface
Uses a WAFER-GH1.25-4PLB connector:
| Pin | Signal | Description |
|---|---|---|
| 1 | DATA | Audio data |
| 2 | SCK | Bit clock |
| 3 | WS | Frame clock (channel select) |
| 4 | GND | Ground |
UART Interfaces
CPU-DBG, CPU-UART, RTSS-DBG, and RTSS-UART all use WAFER-GH1.25-4PLB connectors at 3.3V level:
| Pin | Signal | Description |
|---|---|---|
| 1 | VCC_3VS | 3.3V power |
| 2 | UART_TX | UART transmit |
| 3 | UART_RX | UART receive |
| 4 | GND | Ground |
Usage
After connecting a serial debugging tool (such as MobaXterm or minicom), you can view the boot logs of the CPU and RTSS subsystems.
View the serial devices in the system:
ls /dev/ttyS*View the SPI devices:
ls /dev/spidev*Note
SPI has not yet been enabled in software, so there is currently no /dev/spidev* node in the system. See SPI Interface for details.
Notes
- The UART interfaces are at 3.3V level; do not connect 5V serial devices directly, to avoid damaging the chip.
- Pay attention to level matching when designing external interfaces.
- For high-speed signal interfaces, handle layout routing according to the design requirements to ensure interface performance.