Carrier Board Design Reference
This document provides key guidelines for designing the carrier board for the Rhino Core Q85 intelligent module, helping customers quickly complete the carrier board schematic design and PCB layout.
Connector Selection
The core board connects to the carrier board through the following Panasonic board-to-board connectors:
| Core Board Connector | Model | Carrier Board Mating Part | Pin Count | Pitch |
|---|---|---|---|---|
| J1, J2, J3 | AXK600337YG | AXK500137YG | 100-pin | 0.5mm |
| J4 | AXK680337YG | AXK580137YG | 80-pin | 0.5mm |
When selecting carrier board connectors, ensure the pin count, pitch, and stack height match the core board.
Signal Integrity Design Requirements
Impedance Control
The following high-speed interfaces require impedance control. The carrier board trace impedance should match the core board:
| Interface | Impedance Requirement |
|---|---|
| MIPI DSI | 100Ω differential |
| MIPI CSI | 100Ω differential |
| PCIe Gen3/Gen4 | 85Ω differential |
| USB 3.1 Gen2 | 90Ω differential |
| USB 2.0 | 90Ω differential |
| SDIO (SD 3.0 SDR104) | 50Ω single-ended |
Length Matching
High-speed differential pairs require length matching, with intra-pair length deviation kept within ±5mil. For specific trace length requirements of different interfaces, refer to the appendix of the product specification or contact APLUX FAE.
Interface Design Guidelines
SPI Interface
- The SPI bus level is 1.8V. Pay attention to interface level matching in the carrier board design.
- All SPI interfaces support master mode only; they cannot be used as slaves.
- Each SPI provides only one CS chip-select signal. If multiple SPI slave devices need to be connected, contact us for assistance.
- SPI-to-CAN has been verified and adapted on our carrier boards; it is recommended to reuse it directly for CAN communication needs.
- For sensor devices (accelerometer/gyroscope), use SSC_QUP_SPI.
I2C Interface
- The I2C bus level is 1.8V. Pay attention to level matching in the carrier board design.
- All I2C interfaces have no pull-up resistors on the core board; the carrier board must add pull-ups, with a recommended pull-up resistor of 2.2kΩ.
- It is recommended to reserve 0Ω series resistors on the signal lines and adjust the resistance as needed.
- CCI I2C is dedicated to cameras and cannot be used for other devices. If Always-ON functionality is required, use AON_CCI only.
- SSC_QUP_I2C is dedicated to sensors. For accelerometer/gyroscope devices, use SSC_QUP_I2C.
I2S Interface
- All I2S interfaces can be configured as PCM or TDM, and data channels can be configured as input or output.
SoundWire Interface
- The SoundWire bus topology supports star and daisy-chain configurations.
- The core board has completed software and hardware adaptation for the WCD9385 Codec. If you have Codec requirements, it is recommended to use our carrier board design.
TF Card (SD) Interface
- The SDC signals exposed by the core board are 1.2V level and require the SD-specific level shifter NVT4858UKZ.
- Supports SD v3.0 with a maximum speed of SDR104.
- Contact APLUX FAE for reference circuits.
MIPI CSI Interface
- The carrier board impedance should match the core board (100Ω differential).
- Of the 5 CSI groups, 4 are 4-lane and 1 is 2-lane.
MIPI DSI Interface
- The carrier board impedance should match the core board (100Ω differential).
- Both DSI groups are 4-lane.
- DSI0 supports Split-link mode: DSI0_CLK0 is used for DSI0 Lane 0/1, DSI0_CLK1 for DSI0 Lane 2/3; clocks must not be mixed.
- In Single mode, DSI_CLK1 is left floating.
- The LT8911 (DSI-to-eDP bridge IC) has been verified and adapted on our carrier boards.
PCIe Interface
- AC coupling capacitors should be placed near the TX side. If there is a connector, place them near the connector.
- The carrier board impedance should match the core board (85Ω differential).
- PCIe0 is Gen3 × 2 and PCIe1 is Gen4 × 2.
USB Interface
- The USB signals are compatible with DP signals; DP supports 4 lanes at 8.1Gbps/lane.
- The carrier board impedance should match the core board (90Ω differential).
- USB 3.1 Gen2 supports up to 10Gbps.
Carrier Board Design Checklist
| Check Item | Description | Status |
|---|---|---|
| Connector model | Carrier board connector model matches the core board | ☐ |
| Power design | Stable VBATT 3.5V~4.2V supply, 3.8V recommended | ☐ |
| Level matching | 1.8V I/O level interfaces need a level shifter to connect 3.3V/5V peripherals | ☐ |
| I2C pull-up | Carrier board I2C buses need external 2.2kΩ pull-ups | ☐ |
| SD level shifting | SD signals need 1.2V level shifting using NVT4858UKZ | ☐ |
| Impedance control | High-speed signals (CSI/DSI/PCIe/USB) require impedance matching | ☐ |
| ESD protection | External interfaces need ESD protection devices | ☐ |
| Thermal design | Ensure the core board heat dissipation path is clear; add heatsinks or fans if necessary | ☐ |
| Reset circuit | PM_RESIN_N and KPD_PWR_N must be correctly connected | ☐ |
| Flashing circuit | FORCE_USB_BOOT must be able to be grounded to enter flashing mode | ☐ |
Note
The above are the key points of carrier board design. For complete reference design materials (schematics, PCB source files, layout guidelines), contact APLUX FAE: noah.yang@aidlux.com.