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Mechanical & Thermal Design

Physical Dimensions

ItemParameters
PCBA Dimensions40mm × 40mm (±0.5mm)
Board Thickness1.0mm (±10%)
Mounting Hole Diameter4mm
Screw Hole Specification∮2.2mm × 4 (±10%)

Installation

The core board connects to the carrier board through 4 sets of Panasonic board-to-board connectors. See Interfaces & Pins for the specific connector models. During installation, ensure the connectors are aligned and pressed evenly to avoid poor contact caused by tilting.

ConnectorModelMating Part Model
J1, J2, J3Panasonic AXK600337YGAXK500137YG
J4Panasonic AXK680337YGAXK580137YG

No-Component Area

In the carrier board design, the area below the core board projection (including connectors) must be kept free of components to avoid interference between carrier board components and the components on the bottom of the core board. The height of components on the top side of the core board should be considered in the carrier board layout.

Note

For precise mechanical dimension drawings and no-component area boundaries, contact APLUX FAE for detailed CAD mechanical files: noah.yang@aidlux.com.

Thermal Recommendations

The QCS8550 platform has high power consumption under full load. It is recommended to design a thermal solution based on the actual application scenario:

  • Passive Cooling: Heat from the SoC area of the core board is conducted to the metal enclosure or heatsink through a thermal pad, using natural convection for dissipation.
  • Active Cooling: For high-load scenarios (such as continuous AI inference), it is recommended to add active fan cooling to keep the core board operating temperature below 50°C.
  • Heat Dissipation Path: The top side of the core board (SoC side) is the heat dissipation surface. It is recommended to attach the thermal interface material to the top of the SoC shielding can on the core board.

Environmental Requirements

ItemParameters
Operating Temperature-25°C ~ 50°C
Storage Temperature-30°C ~ 80°C
Relative Humidity0% ~ 95% (non-condensing)

Note

  • This product is not ESD-protected by design; ESD protection must be designed on the carrier board.
  • Pay attention to level matching when designing external interfaces.
  • High-speed signal interfaces should be routed according to the design requirements to ensure interface performance.