Carrier Board Design
This document provides key guidelines for the Rhino Core Q64 smart module carrier board design, helping customers quickly complete the carrier board schematic design and PCB layout.
Connector Selection
The core board connects to the carrier board through the following Panasonic board-to-board connectors:
| Core Board Connector | Model | Carrier Board Mating Part | Pin Count | Pitch |
|---|---|---|---|---|
| J1, J2, J3 | AXK600337YG | AXK500137YG | 100 pins | 0.5mm |
| J4 | AXK680337YG | AXK580137YG | 80 pins | 0.5mm |
When selecting the carrier board connector, make sure the pin count, pitch, and stacking height match the core board.
Signal Integrity Design Requirements
Impedance Control
The following high-speed interfaces require impedance control. The carrier board routing impedance should be consistent with the core board:
| Interface | Impedance Requirement |
|---|---|
| MIPI DSI | Differential 100Ω |
| MIPI CSI | Differential 100Ω |
| eDP | Differential 100Ω |
| PCIe Gen3 | Differential 85Ω |
| USB 3.1 Gen1 | Differential 90Ω |
| USB 2.0 | Differential 90Ω |
| SDIO (SD 3.0 SDR104) | Single-ended 50Ω |
Length Matching Requirements
High-speed differential pairs require length matching, with within-pair length deviation controlled within ±5mil. For specific trace length requirements of different interfaces, refer to the appendix of the product specifications or contact the APLUX FAE team.
Interface Design Guidelines
Serial Port (UART)
- The UART level is 1.8V; pay attention to level matching in the carrier board design.
- The debug UART is for debugging only and must not be used for other functions.
- RS485 / RS232 conversion chips need to be designed on the carrier board.
- For the BT four-wire UART, it is recommended to refer to our matching mainboard design to reduce software development effort.
SPI Interface
- The SPI bus level is 1.8V; pay attention to interface level matching in the carrier board design.
- All SPI interfaces support master mode only and cannot be used as slaves.
- Each SPI has only one reserved CS chip-select signal. If multiple SPI slave devices need to be connected, please consult us.
- SPI-to-CAN has been verified and adapted on our matching mainboard; for CAN communication requirements, it is recommended to reuse it directly.
I2C Interface
- The I2C bus level is 1.8V; pay attention to level matching in the carrier board design.
- There are no pull-ups on the core board for all I2C interfaces; the carrier board must add pull-ups, with a recommended pull-up resistor of 2.2kΩ.
- It is recommended to reserve 0Ω series resistors on the signal lines and adjust the resistance according to actual needs.
- CCI I2C is dedicated to cameras and must not be used for other devices.
- SSC I2C is dedicated to sensors; use SSC I2C for devices such as accelerometers/gyroscopes.
I2S Interface
- All I2S interfaces can be configured as PCM or TDM, and the data channels can be configured as input or output.
SoundWire Interface
- The SoundWire bus topology supports star and daisy-chain configurations.
- The core board has completed software and hardware adaptation for the WCD9385 Codec; if you have Codec requirements, it is recommended to use our carrier board design.
TF Card (SD) Interface
- Supports SD v3.0 with a maximum speed of SDR104 and supports dual-level signaling.
- Card insertion detection is active low. Design the circuit according to the insertion detection logic of the SD card socket used; pull-ups on the signal lines are reserved.
- Contact the APLUX FAE team for the reference circuit.
MIPI CSI Interface
- The carrier board design impedance should be consistent with the core board (differential 100Ω).
- All 4 CSI groups are 4-lane and support D-PHY and C-PHY.
- Our matching carrier board design uses MIPI D-PHY; design C-PHY interfaces yourself if needed.
MIPI DSI Interface
- The carrier board design impedance should be consistent with the core board (differential 100Ω).
- The single DSI group is 4-lane and supports D-PHY and C-PHY.
- Our reference carrier board uses the D-PHY interface.
eDP Interface
- The core board natively supports the 4-lane eDP interface.
- QCS6490 natively supports eDP, so no bridge chip is needed on the carrier board.
PCIe Interface
- AC coupling capacitors: TX AC capacitors are already on the board. If there is a connector, place them close to the connector.
- The carrier board design impedance should be consistent with the core board (differential 85Ω).
- PCIe0 is Gen3 × 1 lane (1 differential pair) and does not support NVMe.
- PCIe1 is Gen3 × 2 lanes (2 differential pairs) and supports NVMe.
USB Interface
- USB0 is USB 3.1 Gen1 (5Gbps), compatible with DP mode and supports DP 4 Lane.
- USB1 is USB 2.0 HS.
- The carrier board design impedance should be consistent with the core board (differential 90Ω).
Carrier Board Design Checklist
| Check Item | Description | Status |
|---|---|---|
| Connector Model | Carrier board connector model matches the core board | ☐ |
| Power Design | Stable VBATT 3.5V~4.2V supply, 3.8V recommended; reserve ≥2×47μF capacitors + TVS diode | ☐ |
| Auto Power-on | A trigger circuit must be designed; cannot be implemented via PM_CBL_PWR_N | ☐ |
| Level Matching | 1.8V I/O level interfaces must connect 3.3V / 5V peripherals through level shifters | ☐ |
| I2C Pull-ups | Carrier board I2C buses need 2.2kΩ pull-ups | ☐ |
| Impedance Control | High-speed signals (CSI/DSI/eDP/PCIe/USB) require impedance matching | ☐ |
| ESD Protection | ESD protection devices must be added to external interfaces | ☐ |
| Thermal Design | Ensure the core board heat dissipation path is clear; add a heatsink or fan if necessary | ☐ |
| Reset Circuit | PM_RESIN_N and KPD_PWR_N must be connected correctly | ☐ |
| Flashing Circuit | FORCE_USB_BOOT (active high) must be pullable high to enter flashing mode | ☐ |
Note
The above are the key points of the carrier board design. For complete reference design materials (schematics, PCB source files, layout guidelines), please contact the APLUX FAE team: noah.yang@aidlux.com.