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Mechanical & Thermal Design

Physical Dimensions

ItemParameter
PCBA Size40mm × 40mm (±0.5mm)
Board Thickness1.0mm (±10%)
Mounting Hole Diameter4mm
Screw Hole Specification∮2.2mm × 4 (±10%)

Installation

The core board connects to the carrier board through 4 sets of Panasonic board-to-board connectors. See Interfaces & Pins for the specific connector models. During installation, ensure the connectors are aligned and pressed evenly to avoid poor contact caused by tilting.

ConnectorModelMating Part Model
J1, J2, J3Panasonic AXK600337YGAXK500137YG
J4Panasonic AXK680337YGAXK580137YG

Keep-Out Area

In the carrier board design, the area under the core board projection (including connectors) should remain a keep-out zone to avoid interference between carrier board components and the components on the bottom of the core board. The height of components on the top side of the core board should be accounted for when laying out the carrier board.

Note

For accurate mechanical dimension drawings and keep-out area ranges, please contact the APLUX FAE team for detailed CAD mechanical files: noah.yang@aidlux.com.

Thermal Dissipation Recommendations

The QCS6490 platform consumes considerable power under full load. It is recommended to design a thermal dissipation solution based on the actual application scenario:

  • Passive Cooling: Use thermal pads to conduct heat from the core board SoC area to a metal enclosure or heatsink, relying on natural convection.
  • Active Cooling: For high-load scenarios (e.g., continuous AI inference), it is recommended to add active fan cooling to ensure the core board operating temperature does not exceed 50°C.
  • Heat Dissipation Path: The top side of the core board (SoC side) is the cooling surface. It is recommended to attach the thermal interface material on top of the SoC shield cover.

Environmental Requirements

ItemParameter
Operating Temperature-25°C ~ 50°C
Storage Temperature-40°C ~ 85°C
Relative Humidity0% ~ 95% (non-condensing)

Note

  • This product does not include ESD protection design; ESD protection must be designed on the carrier board.
  • Pay attention to level matching when designing external interfaces.
  • For high-speed signal interfaces, follow the design requirements for Layout routing to ensure interface performance.