Interface Definitions and Applications

This page summarizes the expansion and debug interfaces of the Rhino Pi IQ9N that are available for secondary development.

Interface List

Interface	Quantity	Connector Model	Level	Purpose
CPU-SPI	1	WAFER-GH1.25-6PLB	3.3V	SPI expansion on the CPU side
RTSS-SPI	1	WAFER-GH1.25-6PLB	3.3V	SPI expansion on the RTSS side
I2S	1	WAFER-GH1.25-4PLB	3.3V	Digital audio output
CPU-DBG	1	WAFER-GH1.25-4PLB	3.3V	CPU debug serial port
CPU-UART	1	WAFER-GH1.25-4PLB	3.3V	CPU functional serial port
RTSS-DBG	1	WAFER-GH1.25-4PLB	3.3V	RTSS debug serial port
RTSS-UART	1	WAFER-GH1.25-4PLB	3.3V	RTSS functional serial port

For the positions of the interfaces on the board, see Debug & Expansion Interfaces.

Pin Definitions

For the positions of the interfaces above on the board, see the interface layout diagram in Rhino Pi IQ9N Interface Description on the first page.

SPI (WAFER-GH1.25-6PLB)

Pin	Signal
1	VCC_3V3
2	MISO
3	MOSI
4	CLK
5	CS
6	GND

CPU-SPI and RTSS-SPI are brought out from mutually independent controllers, so different slave devices can be attached to each.

UART (WAFER-GH1.25-4PLB)

Pin	Signal
1	VCC_3VS
2	UART_TX
3	UART_RX
4	GND

CPU-DBG, CPU-UART, RTSS-DBG, and RTSS-UART are all 3.3V level and share the same pin definitions.

I2S (WAFER-GH1.25-4PLB)

Pin	Signal
1	DATA
2	SCK
3	WS
4	GND

Matching Cables

• The interfaces above are all 1.25 mm pitch sockets; use the corresponding GH1.25 terminal cables to connect them.
• Connector specifications and wire order definitions are subject to official APLUX documentation; incorrect wiring may damage the device.

Device Nodes

After connecting a device, you can view the corresponding nodes in the system:

# Serial ports (4 channels; measured as /dev/ttyS0 ~ /dev/ttyS3)
ls /dev/ttyS*

# Audio devices (onboard I2S sound card and external audio devices)
aplay -l
arecord -l

Note

SPI software enablement has not been completed yet, so there is currently no /dev/spidev* node in the system; for the actual situation, see SPI.

Notes

• All expansion interfaces are 3.3V level; never connect 5V signals directly, and use level shifting when necessary.
• The module has no ESD protection design, so take anti-static precautions when wiring by hand and avoid hot-plugging.
• High-speed signal routing must follow the hardware design requirements; pay attention to impedance and length matching requirements when making custom adapter boards.
• The electrical capabilities and multiplexing relationships of each interface are subject to official APLUX documentation.