SPI

The Rhino Pi IQ9N provides 2 SPI interfaces: CPU-SPI and RTSS-SPI, both using the WAFER-GH1.25-6PLB connector.

Interface Definition

For the positions of CPU-SPI and RTSS-SPI on the board, see the interface layout diagram in Rhino Pi IQ9N Interface Description on the first page.

Pin	Signal	Description
1	VCC_3V3	3.3V power supply
2	MISO	Master input / slave output
3	MOSI	Master output / slave input
4	CLK	Clock
5	CS	Chip select
6	GND	Ground

Testing Notes

[To be added: SPI transmit/receive test method — hardware testing of this SPI channel has not been completed and verified yet; the device node, command-line instructions, and example code will be added once testing confirms it is usable.]

Notes

• The interface is 3.3V level; connecting a 5V slave device directly may cause communication errors or damage the components.
• CPU-SPI and RTSS-SPI are independent controllers; when using them, confirm that your peripheral is attached to the correct bus.
• When increasing the clock frequency, confirm the timing of the slave device at the same time and pay attention to signal integrity.
• For wiring and interface position descriptions, see Debug & Expansion Interfaces.